1 tm an9871.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil americas inc. copyright ?intersil americas inc. 2001, all rights reserved \ operation of the unislic14 family of slics evaluation board functional description evaluation board the hc5514x evaluation board, due to the common pinout of the unislic14 family, is capable of evaluating the performance of the following parts in the unislic14 family (hc55120, hc55121, hc55130, hc55140, hc55142 and hc55150). this evaluation board also has provisions for the evaluation of the 758xx access switch, which is not covered in this application note. for information about the operation of the access switch reference application note an9870 ?peration of the 758xx line card access switch? the sample provided with this board (hc5514x) will illustrate the electrical performance for all members of the family listed above. the board is con?ured to match a 600 ? line impedance, have a minimum loop current of 20ma, a maximum loop current of 30ma, onhook transmission of 0.775v rms , offhook voice transmission of 3.2v peak , and a maximum loop resistance of 1777 ? . for evaluation of the programmability of the hc5514 family, reference the data sheet for calculation of external components. an excel spread sheet can be downloaded from the web for easy calculation of external components (www.intersil.com/telecom/unislic14.xls). the board is equipped with eleven single pole double throw (spdt) switches. the switches control the logic state and performance of the hc5514 and the 758xx access switch. the logic control (c3, c2, c1), shd and gkd/ l vm switches are center open toggle switches. if off-board mode control of the slic is desired, these switches can be set to center open position and driven by logic at the logic terminal port. the logic terminal port is located at the bottom right hand side of the board. the logic control for the access switch (lower left hand side of the board) can also be set to center open position and driven by logic at the logic terminal port if desired. power requirements for the hc5514x power supply connections the hc5514x requires as many as three external power supplies. v bh = -48v (typ), v bl = -24v (typ) and v cc = +5v. if the design requires only two supplies, it is recommended that the v bl supply pin ?at. ground connections the three external power supplies should each be grounded at the evaluation board. features toggle switch programming for logic states monitoring of switch hook detect ( shd) and ground key / line voltage measurement ( gkd_ l vm) via on board leds selectable transmit gain 0db/-6db selectable power sharing single/dual battery operation logic terminal port for easy evaluation in existing systems includes a ring relay for evaluation of ring trip and provisions for evaluation of intersil s 758xx linecard access switch selectable/programmable polarity reversal time programmable 2-wire impedance programmable loop detect threshold programmable onhook and offhook overheads provisions for pulse metering provisions for internal transhybrid balance provisions for line voltage measurement test getting started verify that the sample is oriented in its socket correctly. correct orientation is with pin 1 pointing towards the top of the board (tip and ring terminals to the left). (reference the data sheet for device pinout.) verifying basic slic operation the operation of the sample part can be veri?d by performing the following tests: (the board comes with a standard ring relay. the following set of tests, evaluate the operation of the hc5514x with the ring relay.) 1. power supply current veri?ation forward active and reverse states 2. normal loop feed veri?ation forward active and reverse active states 3. gain veri?ation 4-wire to 2-wire and 2-wire to 4-wire 4. polarity reversal time 5. battery selection/power sharing 6. ring trip veri?ation 7. pulse metering 8. transhybrid balance 9. line voltage measurement test application note february 2001
2 the evaluation of all 9 tests require the following equipment: a 600 ? (1 watt, 1%) load, a 1777 ? (2 watt, 1%) load, a 26.1k ? (1/4 watt, 1%) rdc_rac resistor, two sine wave generators, an ac/dc volt meter, three external supplies (v bh , v bl , v cc ), a dual channel storage oscilloscope, a telephone, bnc to banana adaptor, a battery backed ac source and a dynamic signal analyzer. application tip: when terminating tip and ring, it is handy to assemble terminators using a pomona mdp dual banana plug connector as the terminating resistor receptacle. refer to figure 1 for details. using the termination shown in figure 1 provides an unobtrusive technique for terminating tip and ring while still providing access to both signals using the banana jack feature of the mdp connector. posts are also available that ? into holes a and b, providing a solderable connection for the terminating resistor. test #1, power supply current veri?ation a quick check of the evaluation board and sample is to measure the supply currents. the readings should be similar to the values listed in table 1. the measurements can be made using a series ammeter on each supply, or power supplies with current displays. setup 1. connect the power supplies to the evaluation board. 2. set v bh to -48v, v bl to -24v and v cc to +5v. 3. verify the thermal management switch (s9, located towards the top middle of the board) is in the v bl = v bl position. 4. verify that the pol/rev switch s4 (lower right hand side of the board) is in either the 10ms or 20ms position. 5. con?ure the shd switch (s5) to be in the jack position. this will allow an accurate reading of the v cc current by removing the shd led current. 6. con?ure the gkd_ l vm switch (s6) to be in the bnc position. this will allow an accurate reading of the v cc current by removing the gkd_ l vm led current. 7. con?ure the slic to be in the forward active state (c3 = 0, c2 = 1, c1 = 0). measure the supply currents and compare to those in table 1. 8. terminate tip and ring with a 600 ? load. measure the supply currents and compare to those in table 1. remove 600 ? load. 9. con?ured the slic in the reverse active state (c3 = 1, c2 = 1, c1 = 0). measure the supply currents and compare to those in table 1. repeat step 8. test #2, normal loop feed veri?ation this test veri?s the correct tip and ring voltages in both onhook and offhook forward active and reverse active states. loop current and ground key detect are also veri?d via the onboard shd and gkd_ lvm leds. discussion the hc5514 is designed to have its most positive 2-wire terminal (tip in the forward active state and ring in the reverse active state) ?ed at a set voltage. this set voltage depends upon the required overheads for the application. the most negative 2-wire terminals voltage is dependent upon the load across tip and ring and the programmable current limit. the tip and ring voltages for various loop resistances are shown in figure 2. the tip voltage remains relatively constant as the ring voltage moves to limit the loop current for short loops. when power is applied to the slic, a loop current will ?w from tip to ring through the 600 ? load. loop current detection occurs when this loop current triggers an internal detector that pulls the output of shd low, illuminating the led through the +5v supply. gnd ab figure 1. termination adapter 600 ? table 1. supply currents and power dissipations logic state r l ( ? ) supply voltage (dc) supply current typ (ma) power dissipation (mw) forward active onhook without load v bh = -48v 0.8 38.4 v bl = -24v 0.0001 0.0024 v cc = +5v 2.91 14.5 forward active offhook with 600 ? load v bh = -48v 30.0 1440 v bl = -24v 2.68 64.3 v cc = +5v 4.2 21 reverse active onhook without load v bh = -48v 0.85 40.8 v bl = -24v 0.0001 0.0024 v cc = +5v 2.97 14.8 reverse active offhook with 600 ? load v bh = -48v 29.74 1427 v bl = -24v 1.9 45.6 v cc = +5v 4.27 21.3 application note 9871
3 the ground key detector ( gkd) operation is veri?d by con?uring the hc5514x in the tip open state and grounding the ring pin. grounding the ring pin results in a current that triggers an internal detector that pulls the output of gkd_ lvm low, illuminating the led through the +5v supply. setup (tip and ring voltages) 1. connect the power supplies to the evaluation board. 2. set v bh to -48v, v bl to -24v and v cc to +5v. 3. con?ure the slic to be in the forward active state (c3 = 0, c2 = 1, c1 = 0). 4. verify that the pol/rev pin (lower right hand side of the board) is in either the 10ms or 20ms position. 5. con?ure s5 and s6 switches to be in the led position. 6. disconnect any loads from across tip and ring. 7. measure tip and ring voltages with respect to ground and compare to those in table 2 (onhook). 8. terminate tip and ring with a 600 ? load. 9. measure tip and ring voltages with respect to ground and compare to those in table 2 (600 ? ). 10. con?ure the slic to be in the reverse active state (c3 = 1, c2 = 1, c1 = 0). 11. repeat steps 6 through 9. veri?ation of shd: 1. with the slic in the forward active state, the shd led is on when tip and ring are terminated with 600 ? and off when tip and ring are an open circuit. veri?ation of gkd: 1. con?ure the slic to be in the tip open state (c3 = 1, c2 = 0, c1 = 0). 2. the gkd_ l vm led is on when ring is shorted to ground and off when ring is an open circuit. notice that the shd led will also be on. test #3, gain veri?ation this test will verify the slic is operating properly and that the 4-wire to 2-wire gain (equation 1) is -1.0 (0.0db). the programmable 2-wire to 4-wire transmission gain (equation 2) will also be veri?d by measuring the slic s 4- wire to 4-wire gain with the ptg pin ?ating (a 2-4 is 0.9 (0.91db) and grounded (a 2-4 is 0.56 (-5.0db).) discussion when tip and ring are terminated with 600 ? load, the slic will exhibit unity gain from the 4-wire vrx input pin to across the 2-wire tip and ring pins (v tr ). the db gain is calculated in equation 3. when an open circuit exists, a mismatch occurs and the tip to ring voltage doubles. an easy way to measure the 2-wire to 4-wire transmit gain, without a ?ating signal generator on the 2-wire side, is to measure the 4-wire to 4-wire gain. this way the source can be applied on the ground referenced 4-wire side to the vrx pin. given that the 4-wire to 2-wire gain is approximately one, it follows that the 2-wire to 4-wire transmission gain is also approximately equal to the 4-wire to 4-wire gain. the db 4w to 4w gain is calculated in equation 4. setup (4-wire to 2-wire gain) 1. connect the power supplies to the evaluation board. 2. set v bh to -48v, v bl to -24v and v cc to +5v. 3. con?ure the slic to be in the forward active state (c3 = 0, c2 = 1, c1 = 0). 4. verify that the pol/rev pin s4 (lower right hand side of the board) is in either the 10ms or 20ms position. 5. terminate tip and ring with a 600 ? load. table 2. tip and ring voltages hc5514x logic state r l ( ? ) tip voltage reference d to gnd ring voltage referenced to gnd forward active v bh = -48v v bl = -24v v cc = +5v onhook -2.6 -44.6 offhook 600 -6.3 -24.5 reverse active v bh = -48v v bl = -24v v cc = +5v onhook -44.6 -2.5 offhook 600 -24.4 -6.3 figure 2. tip and ring voltages vs loop resistance tip and ring voltages (v) loop resistance ( ? ) 0 -5 -10 -15 -20 -25 -30 -35 -50 -40 -45 200 600 1000 1400 1800 2000 4k 10k 6k 8k constant loop current region vbh = -48v rd = 41.2k ? roh = 38.3k ? rdc_rac = 19.6k ? rilim = 33.2k ? constant tip to ring voltage region -44.5v -2.5v tip ring a 4-2 = v tr v rx ----------- =-2 z l z l +z tr ------------------------- 2 z l z l z t 200 --------- - 2r p + ?? ?? + ---------------------------------------------- = (eq. 1) a 2-4 = v tx v tr ---------- - = z tr -2r p z tr ----------------------------- (eq. 2) db 4w 2w 20 v tr v rx ----------- log = (eq. 3) db 4w 4w 20 v tx v rx ----------- log = (eq. 4) application note 9871
4 6. connect a sine wave generator, referenced to ground, to the vrx input. 7. set the generator for 1v rms at 1khz. 8. connect an ac voltmeter across tip and ring. veri?ation 1. tip to ring ac voltage of 1v rms when terminated with a 600 ? load. the db (a 4-2 ) gain is approximately 0db. 2. tip to ring ac voltage of 2v rms when not terminated. the db (a 4-2 ) gain is approximately 6db. 3. con?ure the slic to be in the reverse active state (c3 = 1, c2 = 1, c1 = 0) and repeat above test. setup (2-wire to 4-wire gain) 1. connect the power supplies to the evaluation board. 2. set v bh to -48v, v bl to -24v and v cc to +5v. 3. con?ure the slic to be in the forward active state (c3 = 0, c2 = 1, c1 = 0). 4. verify that the pol/rev pin (lower right hand side of the board) is in either the 10ms or 20ms position. 5. terminate tip and ring with a 600 ? load. 6. verify that pin 2 of the ptg jumper (s8, located towards the middle of board near the upper right hand corner of the slic) is ?ating. this condition ?ats the ptg pin. reference section titled ?ayout considerations for more information about the ptg pin. 7. connect a sine wave generator, referenced to ground, to the vrx input. 8. set the generator for 1v rms at 1khz. 9. connect an ac voltmeter, referenced to ground, to the vtx output. veri?ation 1. vtx voltage of 1v rms when pin 2 of the ptg jumper is ?ating. the db (a 2-4 ) gain is approximately -0.9db. 2. vtx voltage of 0.5v rms when pin 2 of the ptg jumper is shorted to pin 1, via the supplied jumper. this condition grounds the ptg pin. the db (a 2-4 ) gain is approximately -5.0db. 3. con?ure the slic to be in the reverse active state (c3 = 1, c2 = 1, c1 = 0) and repeat above test. test #4, polarity reversal time this test will illustrate the operation and programming of the polarity reversal feature. discussion the hc5514x has a programmable polarity reversal time. the evaluation board is equipped with a toggle switch for evaluation of a 10 s and 20 s reversal times. equation 5 gives the formula for programming a desired reversal time. capacitor c4 performs three different functions, ring trip ?tering, polarity reversal time and line voltage measurement. c4 and r7/r10 set the timing for the polarity reversal time. it is recommended that programming of the reversal time be accomplished by changing the value of r7/r10 (see figure 7). setup 1. connect the power supplies to the evaluation board. 2. set v bh to -48v, v bl to -24v and v cc to +5v. 3. con?ure the slic to be in the forward active state (c3 = 0, c2 = 1, c1 = 0). 4. remove generator. 5. verify that the pol/rev pin s4 (lower right hand side of the board) is in either the 10ms or 20ms position. 6. terminate tip and ring with a 600 ? load. 7. select either 10 sor20 s polarity reversal time via the pol / rev switch at the bottom right hand side of the board. 8. monitor the tip and ring voltage levels with a dual channel storage scope. toggle the slic between the forward active state and the reverse active states to trigger the scope. 9. measure the time of reversal. compare results to that listed in table 3. 10. switch the pol / rev (s4) switch to the other reversal time and compare results to that listed in table 3. test #5, battery selection/power sharing discussion (battery selection) this test will illustrate the automatic switching of the supplies by monitoring the v bh and v bl supply currents during onhook and offhook with a 600 ? load across tip and ring. battery selection is a technique, for a two battery supply system, where the slic automatically diverts the loop current to the most appropriate supply for a given loop length. this results in signi?ant power savings and lowers the total power consumption on short loops. this technique is particularly useful if most of the lines are short, and the on hook condition requires a -48v battery. in figure 3, it can be seen that for long loops the majority of the current comes for the high battery supply (v bh ) and for short loops from the low battery supply (v bl ). rsync rev 3.47k ? () reversaltime ms () () = (eq. 5) 34.7k ? rsync rev 73.2k ? > < table 3. polarity reversal time polarity reversal switch setting forward active to reverse reverse active to forward 10 s 10 s 10 s 20 s 20 s 20 s application note 9871
5 setup 1. reference test #1 ?ower supply current veri?ation and the results in table 1. veri?ation 1. notice for the onhook condition (extremely long line) that all the current is provided by v bh. this feature enables onhook transmission on the longest loop for a given battery voltage. 2. notice for a 600 ? load, the current is shared by both v bh and v bl . if tip and ring are shorted, then most of the loop current will come from v bl . 3. notice the same is true for the reverse active state. discussion (power sharing) power sharing is a method of redistributing the power away from the slic in short loop applications. the total system power is the same, but the die temperature of the slic is much lower. power sharing becomes important if the application has a single battery supply (-48v on hook requirements for faxes and modems) and the possibility of high loop currents (reference figure 4). this technique would prevent the slic from getting too hot and thermally shutting down on short loops. the power dissipation in the slic is the sum of the smaller quiescent supply power and the much larger power that results from the loop current. the power that results from the loop current is the loop current times the voltage across the slic. the power sharing resistor (r ps ) reduces the voltage across the slic, and thereby the on-chip power dissipation. the voltage across the slic is reduced by the voltage drop across r ps . this occurs because r ps is in series with the loop current and the negative supply. a mathematical veri?ation follows: given: v bh = v bl = -48v, loop current = 30ma, r l (load across tip and ring) = 600 ? , quiescent battery power = (48v) (0.8ma) = 38.4mw, quiescent vcc power = (5v) (2.7ma) = 13.5mw, power sharing resistor = 600 ? . 1. without power sharing, the on-chip power dissipation would be 952mw (equation 6). 2. with power sharing, the on-chip power dissipation is 412mw (equation 7). a power redistribution of 540mw. on-chip power dissipation without power sharing resistor. on-chip power dissipation with 600 ? power sharing resistor. the design trade-off in using the power sharing resistor is loop length verses on-chip power dissipation. test #6, ring trip veri?ation this test will verify the ringing function of the hc5514x. a telephone, a battery referenced ac signal source, and a bnc to banana adaptor are the only additional hardware required to complete the test. discussion the 600 ? termination is not necessary for this test since the phone provides this nominal impedance when offhook. if the rsync_rev pin is grounded, the ring relay driver pin (rrly) pin goes low after the slic is placed in the ringing state. this will energize the ring relay. the ring relay disconnects tip and ring from the phone and connects the path for the ringing signal. the d t and d r comparator inputs will sense the ?w of dc loop current, enabling the ring trip comparator to sense when the phone is either onhook or offhook. when an offhook condition is detected, the hc5514x will automatically disconnect the ringing signal to the phone at zero current crossing. this reduces impulse noise to the system. refer to the hc5514 subscriber line interface circuit electrical data sheet for more information about the functionality of the ring trip detector. setup 1. connect the power supplies to the evaluation board. 2. set v bh to -48v, v bl to -24v and v cc to +5v. figure 3. battery selection (dual supply systems) loop current (ma) 0 35 30 25 20 15 10 5 1000 900 800 600 700 575 550 525 500 475 450 400 350 300 250 200 150 2000 loop resistance ( ? ) 100 40 vbh = -48v vbl = -24v rilim = 33.2k ? v bl v bh v bh v bl p d v bh () 30ma () 38.4mw 13.5mw rl () 30ma () 2 ++ = (eq. 6) p d 952mw = p d v bh () 30ma () 38.4mw 13.5mw ++ = (eq. 7) r l () 30ma () 2 r ps () 30ma () 2 p d 412mw = figure 4. power sharing (single supply systems) v tx v rx unislic14 tip ring v bl v bh -48v -48v on short loops, the majority of current flows out the v bl pin r ps application note 9871
6 3. con?ure the slic to be in the ringing state (c3 = 0, c2 = 0, c1 = 1). 4. con?ure s5 and s6 to be in the led position. 5. verify that the pol/rev pin s4 (lower right hand side of the board) is in either the 10ms or 20ms position. 6. connect the telephone across tip and ring. 7. ground the rsync_rev terminal. 8. connect battery backed ac (20hz, 90v rms +v bh ) source to ?inging?located just below the tip and ring terminals on the board. veri?ation 1. phone starts ringing when power is applied to the test setup; if not, toggle c1. 2. while ringing and onhook, shd led is not illuminated. 3. while ringing, going offhook will illuminate the shd led. when an offhook condition is detected, the hc5514x will automatically disable the rrly pin (pin goes high) at zero current crossing. this will disable the ring relay and reconnect the tip and ring lines to the phone. 4. when the phone is returned to the onhook condition, shd light will remain on until the logic state of the slic is changed. this precludes any false on hook detection during the transition between off hook (during ringing) and the off hook active state. test #7, pulse metering this test will verify that an offhook 3.1v peak pulse metering signal and a 1.1v peak voice signal can be transmitted simultaneously across a complex loop resistance, on tip and ring, with less than 1% total harmonic distortion. the complex loop impedance is equal to 200 ? at the pulse metering frequency of 16khz, and consist of a series 200 ? resistor and a parallel combination of an 820 ? resistor and a 0.1 f capacitor. programming of the offhook overhead voltage required for simultaneously operation of both signals is achieved by changing the value of rdc_rac to 27.4k ? . a 27.4k ? rdc_rac resistor (provided with kit), two signal generators, the complex load listed above and a dynamic signal analyzer are required to complete this test. setup 1. connect the power supplies to the evaluation board. 2. set v bh to -48v, v bl to -24v and v cc to +5v. 3. con?ure the slic to be in the forward active state (c3 = 0, c2 = 1, c1 = 0). 4. verify that the pol/rev switch s4 (lower right hand side of the board) is in either the 10ms or 20ms position. 5. change r1 resistor rdc_rac to 27.4k ?. 6. verify that pin 2 of the ptg jumper (s8, located towards the middle of board near the upper right hand corner of the slic) is shorted to pin 1. this condition grounds the ptg pin. 7. connect a series 200 ? resistor and a parallel combination of an 820 ? resistor and a 0.1 f capacitor across tip and ring terminals. 8. put a 0.777v rms (1.1v peak ) 1khz signal into the vrx input. 9. put a 0.55v rms 16khz signal into the spm input. (equivalent to 3.1v peak across tip and ring due to gain of 4 from the spm pin to tip and ring.) 10. measure the thd across the complex test load. veri?ation 1. the thd of the 1khz signal is less than 1%. test #8, transhybrid balance this test will illustrate a method of performing transhybrid balance using the ptg pin. the solution is to use the p rogrammable t ransmit g ain pin (ptg) as an input for the receive signal (v rx ). when the ptg pin is connected to a divider network (r14 and r15, figure 5) and the value of r14 and r15 is much less than the internal 500k ? resistor rb, two things happen. first, the transmit gain from v rx to v tx is reduced by half. this is the result of shorting out the bottom 500k ? resistor with the much smaller external resistor. and second, the input signal from v rx is also divided in half by resistors r14 and r15. transhybrid balance occurs when these two, equal but opposite in phase, signals are cancelled at the input to the output buffer. . setup 1. connect the power supplies to the evaluation board. 2. set v bh to -48v, v bl to -24v and v cc to +5v. 3. con?ure the slic to be in the forward active state (c3 = 0, c2 = 1, c1 = 0). 4. verify that the pol/rev pin s4 (lower right hand side of the board) is in either the 10ms or 20ms position. 5. terminate tip and ring with a 600 ? load. 6. verify that pin 2 of the ptg jumper (s8, located towards the middle of board near the upper right hand corner of the slic) is short to pin 3. this condition connects resistors r14 and r15 to the ptg pin. figure 5. transhybrid balance using the ptg pin v tx v rx v tx - + v rx + - 500k 500k 500k ptg + - i x 5 a = 1 i x r14 r15 500k unislic14 output buffer ra rb application note 9871
7 7. connect a sine wave generator, referenced to ground, to the vrx input. 8. set the generator for 1v rms at 1khz. 9. connect an ac voltmeter, referenced to ground, to the vtx output. veri?ation 1. 1. the 4-wire to 4-wire transhybrid balance is about -24db as calculated in equation 8. test #9, line voltage measurement discussion a few of the slics in the unislic14 family feature line voltage measurement (lvm) capability. this feature provides a pulse on the gkd_ l vm output pin that is proportional to the loop voltage. knowing the loop voltage and thus the loop length, other basic cable characteristics such as attenuation and capacitance can be inferred. decisions can be made about gain switching in the codec to overcome line losses and veri?ation of the 2-wire circuit integrity. the lvm function can only be activated in the off hook condition in either the forward or reverse operating states. the lvm uses the ring signal supplied to the slic as a time base generator. the loop resistance is determined by monitoring the pulse width of the output signal on the gkd_ l vm pin. the output signal on the gkd_ l vm pin is a square wave for which the average duration of the low state is proportional to the average voltage between the tip and ring terminals. the loop resistance is determined by the tip to ring voltage and the constant loop current. reference figure 6. although the logic state changes to the test active state when performing this test, the slic is still powered up in the active state (forward or reverse) and the subscriber is unaware the measurement is being taken. setup 1. connect the power supplies to the evaluation board. 2. set v bh to -48v, v bl to -24v and v cc to +5v. 3. con?ure the slic to be in the test active state (c3 = 0, c2 = 1, c1 = 1). 4. verify that the pol/rev pin s4 (lower right hand side of the board) is in either the 10ms or 20ms position. 5. terminate tip and ring with a 600 ? load. 6. connect battery backed ac (20hz, 90v rms +v bh ) source to ring gen input located just below the tip and ring terminals on the board. 7. verify that pin 2 of the ptg jumper (s8, located towards the middle of board near the upper right hand corner of the slic) is ?ating. 8. monitor the output signal on the gkd_ l vm pin with a scope. veri?ation 1. the output signal on the gkd_ l vm pin is a square wave for which the average duration of the low state is proportional to the average voltage between the tip and ring terminals. 2. change the load to 1777 ? load and notice the change in the pulse width of the gkd_ l vm pulse. 3. notice the same is true for the test reversal active state (c3 = 1, c2 = 1, c1 = 1). functional circuit component descriptions a brief description of each component is provided below. the components will be grouped by function to provide further insight into the operation of the hc5514x board. db 4w 4w 20 v tx v rx ----------- log = (eq. 8) figure 6. operation of the line voltage measurement circuit tip ring dt dr ring gen gkd_ l vm ring gen freq pulse width proportional to loop length pulse loop length width unislic14 table 4. two wire side, tip and ring rp1, rp2 protection resistors used for limiting the current into the transient voltage suppressor in the event of a surge. u2 secondary surge protection. table 5. power sharing r13, s9 r13 (r ps ) is used to provide off-chip power dissipation to prevent the slic from going into thermal shutdown in short loop high power applications. table 6. programmable features of the hc5514x r1, c7 r1 is used to set the overhead voltage. c7 provides filtering for the dc loop and anti clipping circuitry. c3 cdc provides filtering of the dc loop. r4 rd resistor. used to set the offhook detect threshold. r5 roh resistor. used to set the minimum loop current with maximum overhead voltage. application note 9871
8 layout considerations systems with dual supplies (v bh and v bl ) if the v bl supply is not derived from the v bh supply, it is recommended that an additional diode be placed in series with the v bh supply. the orientation of this diode is anode on pin 8 of the device and cathode to the external supply. this external diode will inhibit large currents and potential damage to the slic, in the event the v bh supply is shorted to gnd. if v bl is derived from v bh then this diode is not required. floating the ptg pin the ptg pin is a high impedance pin (500k ? ) that is used to program the 2-wire to 4-wire gain to either 0db or -6db. if 0db is required, it is necessary to ?at the ptg pin. the pc board interconnect should be as short as possible to minimize stray capacitance on this pin. stray capacitance on this pin forms a low pass ?ter and will cause the 2-wire to 4-wire gain to roll off at the higher frequencies. if a 2-wire to 4-wire gain of -6db is required, the ptg pin should be grounded as close to the device as possible. spm pin for optimum performance, the pc board interconnect to the spm pin should be as short as possible. if pulses metering is not being used, then this pin should be grounded as close to the device pin as possible. rlim pin the current limiting resistor r lim needs to be as close to the rlim pin as possible. layout of the 2-wire impedance matching resistor z t proper connection to the zt pin is to have the external z t network as close to the device pin as possible. the zt pin is a high impedance pin that is used to set the proper feedback for matching the impedance of the 2-wire side. this will eliminate circuit board capacitance on this pin to maintain the 2-wire return loss across frequency. r7, r9, r10, s4 rsync_rev resistor. used to set the polarity reversal time with c4 and provide an input for ring synchronization. r6 rilim resistor. used to set the current limit. r14, r15 used for transhybrid balance of the voice signal. r2, r3, r11, r12 used in the detection of ring trip. r8, r16, c13 z t resistor. used in the impedances matching of the 2-wire side. r17, r18, s5, s6 current limiting resistors for shd and gkd_ lvm leds. s8 switch 8 is used to program the 2-wire to 4-wire transmission gain and 4-wire to 4-wire transhybrid balance. c4 crt_rev_ lvm capacitor. filters ring trip and is used in setting both the polarity reversal time and line voltage measurement. c2 ch capacitor. provides ac and dc separation on the 2-wire side. s1, s2, s3 toggle switches to set the logic state of the slic. table 7. supply decoupling capacitors c1, c5, c6, c10, c11, c12 supply decoupling capacitors. table 6. programmable features of the hc5514x application note 9871
9 demo board schematic tip ring vtx vrx zt rsync_rev ilim roh rd shd gkd_ l vm c1 c2 c3 vcc rrly ch gnd vbh vbl rdc_rac cdc dr dt crt_rev_ l vm c 1 +5v +12v relay c 2 -24v r 13 -48v c 3 r p1 ring tip r p2 r 2 r 3 vbat ring generator r 4 r 6 r 5 c 4 r 12 u1 u2 2 3 5 6 7 8 9 10 11 12 13 14 20 1 4 15 16 17 18 19 21 22 23 24 26 28 ptg agnd spm 12/16khz pulse metering input signal c 10 c 11 c 6 c 5 c 12 v bl = v bl v bl = v bh rj-11 j15 r 1 c 7 r 11 logic terminal port c2 c1 c3 shd spst center off spst gkd_ l vm led d2 led on det low +5v ? figure 7. unislic14 demo board schematic ?? ? spst shd led d1 led on det low gkd l vm r 7 spst r 10 s1 s2 s3 s4 s5 s6 20ms 10ms h l j11 r 9 j9 j10 r 8 r 16 c 13 25 j5, j6 j8, j7 j13 r 17 r 18 j2 j1 j3 j4 j12 s9 +5v c 8 c 9 + - tp1 tp2 tp3 r 15 2 r 14 test in test out latch tsd 758xx access switch control unislic14 control 1 s8 test in test out latch tsd +5v s12 s11 s10 s7 k1 4 13 6 11 8 9 12 14 10 p4 p3 p2 p1 pina 16 1 tip test out ring test out tip test in ring test in 2 3 5 7 h l h l h l h d 3 optional 3 table 8. basic application circuit component list component value tolerance rating u1 - slic unislic14 family n/a n/a u2 - dual asymmetrical transient voltage suppressor tisp1082f3 n/a n/a rp1, rp2 (line feed resistors) 30 ? matched 1% 2.0w r1 (rdc_rac) r = 50*rfeed, rfeed = 381 ? 21.0k ? 1% 1/16w r2, r3 (input current limiting resistors for dt and dr) 2m ? 1% 1/16w r4 (rd resistor) r = 500/i sh, i sh = 9.78ma 41.2k ? 1% 1/16w r5 (roh resistor) r = 500/iloop(min)-i sh- (iloop(min) = 20ma, i sh- 6.54ma) 38.3k ? 1% 1/16w r6 (r ilim resistor) r = 1000/ilim (ilim = 30ma) 33.2k ? 1% 1/16w application note 9871
10 all intersil products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation s quality certi?ations can be viewed at website www .intersil.com/quality/iso .asp. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or specifications at a ny time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to b e accurate and reliable. how- ever, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties wh ich may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil ltd. 8f-2, 96, sec. 1, chien-kuo north, taipei, taiwan 104 republic of china tel: 886-2-2515-8508 fax: 886-2-2515-8369 r7 (rsync_rev resistors) r = 3.47k/ s (10 s) 34.8k ? 1% 1/16w r8 (rzt, 2-wire impedance matching resistor) r = 200(zo-2rf) z0 = 600 ? , rf = 30 ? 107k ? 1% 1/4w r9 (current limit resistor for ring sync pulse) 49.9k ? 1% 1/16 w r10 (rsync_rev resistor) r = 3.47k/ s (2 s) 69.8k ? 1% 1/16 w r11 (series resistor to simulate loop length during ringing) 600 ? 1% 2w r12 (sense resistor for dc current during ringing) 400 ? 1% 2w r13 (r ps , power sharing resistor) open - - r14, r15 (transhybrid resistors) 10k ? 1% 1/16w r16, c13 (for matching a complex 2-wire impedance) r = 0 ? c13 = open -- r17, r18 (current limiting resistors for leds) 510 5% 1/4w c1, c5 0.01 f 20% 50v c2 0.1 f 20% 10v c3 4.7 f 10% 50v or (v bh /2) c4, c7 0.47 f 20% 10v c6 0.01 f 20% 100v c8, c9 2200pf 20% 100v c10, c12 0.1 f 20% 50v c11 0.1 f 20% 100v d1, d2 ( shd and gkd_ lvm leds) red - - d3, recommended if the v bl supply is not derived from the v bh supply. 1n4004 - - design parameters : switch hook threshold = 12ma, loop current limit = 30ma, synthesize device impedance = 600-60 = 540 ? , with 30 ? protection resistors, impedance across tip and ring terminals = 600 ? . where applicable, these component values apply to the basic application circuits for the hc55120, hc55121, hc55130, hc55140, hc55142 and hc55150. pins not shown in the basic application circuit are no connect (nc) pins. table 8. basic application circuit component list (continued) component value tolerance rating application note 9871
|
